Our CEO, Jonathan Graf, is giving an invited visionary talk at IEEE HOST 2023 tomorrow morning. Come on out and hear what he has to say!
Topic Title: Verify the Bits that Fly
Topic Abstract: The bitstream is the only representation of an FPGA design that "flies" – that is deployed with the device – so why don't we verify them? Programmable and adaptive computing devices, including FPGAs and their complex modern MPSoC variants, present novel challenges to hardware-oriented security and trust. The function of FPGA hardware is not fully realized until programmed with a bitstream that implements a specific application at runtime. The verification of this bitstream is often overlooked, as it is too hardware-like for traditional software verification and too software-like for traditional hardware verification. As a result, substantially all EDA-driven FPGA verification takes place on RTL or netlist models of the design but not on the bitstream that gets deployed. Further non-technical difficulties arise from the legal challenges associated with the intellectual property embodied not only in the bitstream contents but also in the interpretation of bitstream formats. For 17 years, under both government and private funding, Dr. Jonathan Graf has led teams that have produced a variety of solutions to this challenge. In this visionary talk, Jon will tell the story of developing approaches to bitstream verification: the strategies, the dead ends, the hurdles, the policies, the industries with interest, and the current solution. The talk concludes with a discussion of two just-announced EDA software tools from Graf Research, entitled Enverite™ PV-Bit™ and Trace™. These interoperate with traditional EDA tools to provide security assurances for the FPGA bitstream, the “bits that fly.”