Graf Research will be demonstrating the Enverite EDA suite at GOMACTech 2025. Stop by booth 304 in Pasadena, California, from March 18-19, to see a demonstration of Enverite PV-Bit performing FPGA bitstream verification. For more information about GOMACTech 2025, visit their website here.
We’re also presenting three papers at GOMACTech 2025. Our papers discuss the use of the EnsofIC Attest platform for non-destructive evaluation of counterfeit FPGAs (P.110), the use of Benches laboratory management software for system-level fault injection (P.60), and how Enverite PV-Bit verification can be paired with Siemens Questa Equivalent FPGA to improve FPGA safety and security policy compliance.
GOMACTech 2025 Multidisciplinary Approaches to Security
March 20, 2025, 8:20-10:00 AM
FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking
Jonathan Graf, Margaret Winslow, Evan Drinkert, Kevin Urish, and John Hallman
Abstract: Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require the ability to prove the design in an FPGA bitstream matches the anticipated function and structure specified in a designer’s source. Until recently, there were no commercial tools to meet these requirements. Now, emerging tools for bitstream equivalence checking can be paired with established tools for logic equivalence checking to create a verification chain that satisfies these new policy demands. This paper explores three example safety and security policies that call for such verification. A demonstration design is evaluated with logic and bitstream equivalence checking tools, and the output files are enumerated to seamlessly link the conclusions of each tool to policy requirements. Finally, additional assurance requirements that can be met by pairing bitstream equivalence checking tools with other verification techniques are explored.
GOMACTech 2025 Poster Session
March 20, 2025, 10:30-12:00 PM
Towards Synthetic Data Generation for Characterization of FPGAs
Whitney Batchelor, Cody Crofford, Margaret Winslow, Mia Taylor, Kevin Paar, James Koiner, Scott Harper
Abstract: Both the increasing use of machine learning to reason over features relevant to microelectronics and the ongoing threats to the microelectronics supply chain necessitate the need to explore novel methods for characterizing and identifying known good microelectronic devices. Unfortunately, obtaining a statistically relevant number of devices for evaluation is infeasible due to cost and supply chain issues. This leads to a constant deficit in data obtained from good devices that could be used for machine learning reasoning or known good device characterization. Synthetic data generation for use in machine learning training is growing in popularity but comes with its own set of challenges. Here, we present a method for synthetically generating field programmable gate array data that can not only be used to train models for our FPGA counterfeit device detection solution but generally used as characterization data for known good FPGAs.
System-Level Fault Injection on Heterogeneous System-on-Chips
Edward Carlisle IV, James Koiner, Evan Ezell, Scott Harper
Abstract: This paper presents a system-level approach to fault injection on heterogeneous System-on-Chip devices. Our approach simultaneously targets multiple resource types while taking care to maintain transparency of the fault injector and minimize constraints on the end user design. The approach integrates with the Benches laboratory management platform to enable fully automated operation and provide campaign analysis features. The platform can also be leveraged to automate radiation testing.
