PAINE 2024 Poster Presentation on Benches Laboratory Automation

Dr. Ed Carlisle IV will present a poster titled "Improving Workforce Development with Laboratory Automation" at PAINE 2024. The session will take place on November 12, from 4:50 pm to 5:50 pm. Attendees can explore innovative approaches to enhancing workforce training through automation. For more information and registration, visit PAINE 2024

Improving Workforce Development with Laboratory Automation

Edward Carlisle IV, Scott Harper, Jonathan Graf

Abstract: Workforce development efforts that include laboratory components face many challenges, including budget constraints and limited access to equipment. We define the desired capabilities of a laboratory automation platform that can help overcome these challenges and expand the reach of workforce development efforts, accelerating the growth of a well-qualified workforce. This paper presents an automated microelectronics lab experimentation platform called Benches. We describe how Benches incorporates many of these desired features and provides additional benefits for workforce development efforts.

Learn about the Enverite EDA Suite at AMD Security Working Group 2024 Partner Showcases!

Graf Research is attending all three AMD Security Working Group 2024 events. We will have a booth at each Partner Showcase where attendees can discuss how the Enverite EDA suite addresses their specific FPGA security needs. Don't forget to register for the AMD Security Working Groups and attend the Partner Showcase events:

  • Longmont, CO, on Tuesday, October 15, 2024, from 6:00-9:00pm

  • Washington, DC, on Wednesday, November 13, 2024, from 5:30-8:30pm

  • Munich, Germany, on Tuesday, December 10, 2024, from 5:30-8:30pm

Graf Research Presents at Siemens osmosis 2024

On October 17th, Graf Research is presenting at the Siemens osmosis 2024 event in Munich, Germany. Dr. Jonathan Graf will share insights into how the Enverite PV-Bit verification process drives design assurance into the deployed bitstream during his talk titled "Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance." This event focuses on how EDA techniques overcome verification challenges and offers a platform for connecting with experts in the field. Registration for the conference is still open, and attendees can secure their spot through Siemens EDA Events.

Dr. Jonathan Graf Presents at 2024 FPL Conference in Turin, Italy

Dr. Jonathan Graf, CEO of Graf Research, is presenting an industrial talk at the 2024 Field Programmable Logic and Applications (FPL) Conference in Turin, Italy, on September 4th. The conference, known for bringing together leading experts in the field of programmable logic, provides a platform for Dr. Graf to discuss critical advancements in the field.

In his talk, titled "Bitstream Equivalence Checking: Verify the Bits that Fly," Dr. Graf will focus on the importance of robust bitstream verification techniques, particularly as FPGA complexity increases and their use in critical applications expands. Following his presentation, Dr. Graf will be available at the Graf Research exhibit to discuss our Enverite EDA tool suite and the future of bitstream verification.

Graf Research's involvement in FPL 2024 reflects our ongoing commitment to innovation in programmable logic and FPGA technology. For more information about the conference, visit the official FPL website.

GVSETS 2024 Presentation - Challenges and Mitigations for Data Remanence in FPGA Based Systems

Congratulations to Kevin Paar for presenting an outstanding paper on "Challenges and Mitigations for Data Remanence in FPGA Based Systems" during the Modular Open Systems Approach session at GVSETS 2024. The presentation was an insightful exploration of the critical issue of data remanence in field-programmable gate arrays, a topic of growing importance in today’s rapidly evolving technological landscape. This presentation not only highlighted key technical considerations but also underscored the importance of innovation in maintaining data security and integrity.

 

For those who missed it, we highly recommend reviewing the presentation paper here to gain valuable insights. Congratulations once again to Kevin Paar on a remarkable presentation!

Graf Research to Showcase Enverite PV-Bit at DAC 2024

Graf Research Corporation is set to exhibit at the Design Automation Conference (DAC) 2024, which will be held from June 23-27 in San Francisco. At this leading conference for design and automation of electronic systems, Graf Research will highlight their Enverite PV-Bit verification EDA tool.

Attendees will have the opportunity to see demonstrations of Enverite PV-Bit verifying the equivalence between an FPGA netlist and its corresponding bitstream. This demonstration highlights the impact Enverite PV-Bit verification has on hardware safety and security that is of interest to this community.

For more information on DAC 2024, please visit their website.

Graf Research to Attend AMD Premier Partner Summit in San Jose

 We are excited to announce that Graf Research will be attending the AMD Premier Partner Summit in San Jose from June 18-20. This event provides a unique opportunity for us to engage with fellow AMD partners, explore product synergies, and showcase our cutting-edge Enverite PV-Bit verification tool.

The summit promises to be an excellent platform for learning, networking, and collaboration. We look forward to sharing insights, learning from industry leaders, and finding new ways to enhance our products and services.

For more information about our Enverite PV-Bit verification tool, click here.

Graf Research to Exhibit Enverite PV-Bit Verification and the Benches Platform at SEE/MAPLD 2024

Graf Research Corporation is excited to announce its participation in the upcoming 33rd edition of the Single Event Effects (SEE) and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop. This prestigious event will take place from May 13th to 17th, 2024, in San Diego, California. Graf Research will feature two key products at their booth: Enverite PV-Bit verification software and the Benches platform.

Enverite PV-Bit verification is a sophisticated EDA tool tailored for ensuring the equivalence between FPGA netlists and their corresponding bitstreams, addressing a crucial need in hardware design and security.

Benches platform serves as a comprehensive laboratory information management and control system. It is uniquely capable of orchestrating complex interactions and managing configurations among various lab equipment, streamlining laboratory operations significantly.

During the exhibit, Graf Research will offer software demonstrations, allowing attendees to see firsthand how these tools can enhance their operations. For more details about Graf Research’s innovative tools and their participation in the workshop, please visit the SEE/MAPLD website, Enverite PV-Bit, and Benches.

Graf Research to Attend HOST 2024

Graf Research Corporation will be attending the HOST 2024 conference, scheduled for May 6 - 9, 2024, in Washington DC, USA. This premier event in hardware-oriented security and trust will feature leading industry and academic professionals discussing crucial advancements in hardware security. Our presence at this event highlights our commitment to enhancing security measures in the industry. For more details on HOST 2024, please visit their website.

Graf Research and Virginia Tech Showcase Explainable AI Techniques at IEEE ICMLCN 2024

Graf Research and Virginia Tech are presenting a poster at the IEEE International Conference on Machine Learning for Communication and Networking (IEEE ICMLCN) 2024 in Stockholm, Sweden. The paper, titled "Exploring Explainable AI Techniques for Radio Frequency Machine Learning," is featured in Interactive Session 9 on Learning Communication Signal Processing on Wednesday, May 8th, from 1:30pm to 2:30pm.

The presentation highlights the challenges and solutions in interpreting complex deep learning models used in wireless radio frequency communications. The focus is on explainable artificial intelligence (XAI) techniques to demystify model decisions, specifically using attribution methods to assess the influence of inputs on outputs across different data modalities. This collaboration emphasizes the importance of transparency in AI systems, enhancing trust and understanding in advanced machine learning applications.

For additional details about the conference, visit IEEE ICMLCN 2024.

IEEE ICMLCN 2024 Interactive Session 9: Learning Communication Signal Processing

May 8, 2024, 1:30-2:30pm 

Exploring Explainable AI Techniques for Radio Frequency Machine Learning

Stephen Adams (Virginia Tech, USA); Mia Taylor, Cody Crofford, Scott Harper, and Whitney Batchelor (Graf Research Corporation, USA); William C Headley (Virginia Tech, USA)

Abstract: Deep learning models are increasingly being used to solve complex wireless radio frequency communications problems. These state-of-the-art machine learning models have demonstrated superior performance over traditional methods when signal and environmental parameters are unknown a priori. However, due to the complexity of the architecture and the number of parameters, deep learning models are difficult to interpret. This opacity can lead to difficulties during testing and a lack of trust by the user. Explainable artificial intelligence (XAI) techniques can provide estimates for the impact an input has on the output of a model. In this study, we apply a wide range of common attribution techniques, a subset of XAI that focuses on estimating the contribution of each input to an output of a model, to simple wireless communications problems over two different data modalities (raw IQ and spectrogram images) and show how estimates of attributions could be used for test and evaluation.

Presenting Enverite PV-Bit at Siemens osmosis A&D 2024

Siemens osmosis Aerospace and Defense 2024

Dr. Jonathan Graf will be presenting at Siemens osmosis A&D 2024 tomorrow, April 23, 2024, at 2:00pm EST. We are discussing the pairing of Enverite PV-Bit bitstream verification with Siemens Questa Apps to enhance FPGA build flow assurance. Join us at this virtual conference by registering here.

Visit Graf Research's Booth at DoD Anti-Tamper Conference 2024

We are excited to announce that Graf Research will be demonstrating Enverite PV-Bit verification at the DoD Anti-Tamper Conference 2024. Make sure to stop by our booth to in Laurel, Maryland, from April 2-4, 2024.

Enverite EDA offers a comprehensive suite of tools designed to address the critical challenges facing FPGA designers in ensuring the security, integrity, and assurance within their designs. Attendees at DoD Anti-Tamper Conference 2024 will have the opportunity to see a demonstration of Enverite PV-Bit verification. Engage with our experts at the booth and discuss PV-Bit verification of bitstream integrity, or other Enverite features. The Enverite EDA suite also offers the Trace archiver for tamper-evident digital thread creation and the Retrace auditor for automated auditing and reproduction of traced builds.

FPGA designers seeking to enhance their design assurance process can acquire Enverite EDA and unlock its full potential to streamline workflows, mitigate risks, and deliver mission-critical FPGA designs with unmatched assurance.

Graf Research is also presenting “Automating Hardware Trojan Insertion for Producing a Trusted & Assured Microelectronics Benchmark Dataset,” by James Koiner, Kevin Paar, Michael Blacconiere, Margaret Winslow, Scott Harper, and Jonathan Graf at the DoD Anti-Tamper Conference.

See a Demonstration of Enverite PV-Bit at DATE 2024

We are excited to announce that Graf Research will be demonstrating Enverite PV-Bit verification at DATE 2024. Make sure to stop by our table to in Valencia, Spain, from March 25-27, 2024.

Enverite EDA offers a comprehensive suite of tools designed to address the critical challenges facing FPGA designers in ensuring the security, integrity, and assurance within their designs. Attendees at DATE 2024 will have the opportunity to see a demonstration of Enverite PV-Bit verification. Engage with our experts at the table and discuss PV-Bit verification of bitstream integrity, or other Enverite features. The Enverite EDA suite also offers the Trace archiver for tamper-evident digital thread creation and the Retrace auditor for automated auditing and reproduction of traced builds.

FPGA designers seeking to enhance their design assurance process can acquire Enverite EDA and unlock its full potential to streamline workflows, mitigate risks, and deliver mission-critical FPGA designs with unmatched assurance.

See Press Release for more information.

Visit Graf Research in Booth 719 at GOMACTech 2024!

We are excited to announce that Graf Research will be demonstrating Enverite PV-Bit verification in booth 719 at GOMACTech 2024. Make sure to stop by our booth to in Charleston, South Carolina, from March 19-20, 2024.

Enverite EDA offers a comprehensive suite of tools designed to address the critical challenges facing FPGA designers in ensuring the security, integrity, and assurance within their designs. Attendees at GOMACTech 2024 will have the opportunity to see a demonstration of Enverite PV-Bit verification. Engage with our experts at the booth and discuss PV-Bit verification of bitstream integrity, or other Enverite features. The Enverite EDA suite also offers the Trace archiver for tamper-evident digital thread creation and the Retrace auditor for automated auditing and reproduction of traced builds.

FPGA designers seeking to enhance their design assurance process can acquire Enverite EDA and unlock its full potential to streamline workflows, mitigate risks, and deliver mission-critical FPGA designs with unmatched assurance.

See Press Release for more information.

We’re also presenting two papers at GOMACTech 2024 in March – a poster and a presentation. Our papers discuss our EnsofIC Attest platform for non-destructive evaluation of counterfeit FPGAs and the role of EDA, including our Enverite EDA suite, in accelerating the development of high assurance FPGAs.

GOMACTech 2024 Nontraditional Approaches to Trust Session

March 19, 2024, 1:30-3:10 PM

Non-Destructive Evaluation of Repackaged Counterfeit FPGAs via Machine Learning

Whitney Batchelor, James Koiner, Cody Crofford, Kevin Paar, Margaret Winslow, Mia Taylor, Scott Harper

Abstract: With ongoing microelectronic supply chain issues, the demand for genuine field-programmable gate arrays (FPGAs) is increasing – but so is the occurrence of counterfeit devices. Frequently, devices are used, salvaged from old systems, and repackaged as new. These recycled devices represent the largest class of counterfeit devices and are becoming more rampant. Therefore, it is often necessary to test whether a device is counterfeit before employing it in a new system. Current methods for evaluating the genuine nature of devices are frequently destructive, allowing for only small sample testing within lots.  Other methods require complex external equipment and cannot be readily deployed throughout the supply chain. Graf Research Corporation has developed a methodology for using telemetry bitstreams to characterize an FPGA device and subsequently classify whether a device is a repackaged counterfeit via statistical and machine learning models. The new method utilizes minimal external equipment, is non-destructive, and can be employed at any point throughout the supply chain.

GOMACTech 2024 Poster Session

March 21, 2024, 10:30-12:00 PM

The Role of EDA in FPGA Assurance Best Practices

Margaret Winslow, Jonathan Graf, Whitney Batchelor, Scott Harper, Kevin Paar, Ali Asgar Sohanghpurwala

Abstract: Developing assured microelectronics requires coordination throughout the lifecycle of the device to ensure that necessary assurance policy, guidance, and/or best practices are met. Assurance practices recommended by the recently-published DoD Microelectronics: FPGA Level of Assurance 1 Best Practices and related guidance for higher levels of assurance (LoAs) can be categorized such that programs can delegate assurance tasks across personnel within a program. A significant portion of assurance practices remain dependent on the actions of the development team, however.  This paper explores which of the assurance practices that fall to the development team are automatable using Electronic Design Automation (EDA) tools and which involve more manual interventions and practices, highlighting specific tools of interest to the FPGA assurance community.  This work concludes that all assurance tasks left to the development team are accelerable with traditional and emerging EDA tools, making compliance with LoA best practices a tractable challenge.

Graf Research Hosts All-Company Event in Blacksburg, VA

Graf Research Corporation hosted its fifth annual All-Company Event. The whole team met at our headquarters in Blacksburg, VA, for thought provoking presentations and discussions, team-building activities, and delicious food and refreshments. After meeting hours, the team headed to the Black Hen restaurant for great food and conversations. We also had an event at McClain’s for appetizers, bowling, and games.

The whole team is excited to get back to work on product development and research fueled by the new ideas generated at our all-company meeting. We are so thankful for our team of innovative thinkers, and we eagerly anticipate another great year of unleashing innovation at Graf Research Corporation!

IEEE PAINE 2023 - Attest: Non-Destructive Identification of Counterfeit FPGA Devices

We have a poster presentation at IEEE PAINE 2023 in Huntsville, AL on October 24, 2023. Come learn about our Enforte™ Attest™ device verification tool!

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Attest: Non-Destructive Identification of Counterfeit FPGA Devices

Whitney Batchelor, James Koiner, Cody Crofford, Kevin Paar, Margaret Winslow, Mia Taylor, Scott Harper, Ph.D.

Abstract: With ongoing microelectronic supply chain issues, the demand for genuine field-programmable gate arrays (FPGAs) is increasing – but so is the occurrence of counterfeit devices. Frequently, devices are used, salvaged from old systems, and repackaged as new. These recycled devices represent the largest class of counterfeit devices and are becoming more rampant. Therefore, it is often necessary to test whether a device is counterfeit before employing it in a new system. Current methods for evaluating the genuine nature of devices are frequently destructive, allowing for only small sample testing within lots.  Other methods require complex external equipment and cannot be readily deployed throughout the supply chain. Graf Research Corporation has developed a methodology for using telemetry bitstreams to characterize an FPGA device and subsequently classify whether a device is a repackaged counterfeit via statistical and machine learning models. The new method utilizes minimal external equipment, is non-destructive, and can be employed at any point throughout the supply chain.  

Come See us at DAC 2023

DAC 2023 is in full swing! Come on out and see us to learn how Enverite PV-Bit and Trace can help assure your FPGA designs!

Dr. Graf to Deliver Visionary Talk at IEEE HOST 2023

Our CEO, Jonathan Graf, is giving an invited visionary talk at IEEE HOST 2023 tomorrow morning. Come on out and hear what he has to say!

Topic Title: Verify the Bits that Fly

Topic Abstract: The bitstream is the only representation of an FPGA design that "flies" – that is deployed with the device – so why don't we verify them?  Programmable and adaptive computing devices, including FPGAs and their complex modern MPSoC variants, present novel challenges to hardware-oriented security and trust.  The function of FPGA hardware is not fully realized until programmed with a bitstream that implements a specific application at runtime.  The verification of this bitstream is often overlooked, as it is too hardware-like for traditional software verification and too software-like for traditional hardware verification.  As a result, substantially all EDA-driven FPGA verification takes place on RTL or netlist models of the design but not on the bitstream that gets deployed.  Further non-technical difficulties arise from the legal challenges associated with the intellectual property embodied not only in the bitstream contents but also in the interpretation of bitstream formats. For 17 years, under both government and private funding, Dr. Jonathan Graf has led teams that have produced a variety of solutions to this challenge.  In this visionary talk, Jon will tell the story of developing approaches to bitstream verification: the strategies, the dead ends, the hurdles, the policies, the industries with interest, and the current solution.  The talk concludes with a discussion of two just-announced EDA software tools from Graf Research, entitled Enverite™ PV-Bit™ and Trace™. These interoperate with traditional EDA tools to provide security assurances for the FPGA bitstream, the “bits that fly.”