We are excited to announce that Graf Research will be demonstrating Enverite PV-Bit verification at the DoD Anti-Tamper Conference 2024. Make sure to stop by our booth to in Laurel, Maryland, from April 2-4, 2024.
Enverite EDA offers a comprehensive suite of tools designed to address the critical challenges facing FPGA designers in ensuring the security, integrity, and assurance within their designs. Attendees at DoD Anti-Tamper Conference 2024 will have the opportunity to see a demonstration of Enverite PV-Bit verification. Engage with our experts at the booth and discuss PV-Bit verification of bitstream integrity, or other Enverite features. The Enverite EDA suite also offers the Trace archiver for tamper-evident digital thread creation and the Retrace auditor for automated auditing and reproduction of traced builds.
FPGA designers seeking to enhance their design assurance process can acquire Enverite EDA and unlock its full potential to streamline workflows, mitigate risks, and deliver mission-critical FPGA designs with unmatched assurance.
Graf Research is also presenting “Automating Hardware Trojan Insertion for Producing a Trusted & Assured Microelectronics Benchmark Dataset,” by James Koiner, Kevin Paar, Michael Blacconiere, Margaret Winslow, Scott Harper, and Jonathan Graf at the DoD Anti-Tamper Conference.