Publications

GOMAC 2025

W. Batchelor, C. Crofford, M. Winslow, M. Taylor, K. Paar, J. Koiner, S. Harper, “Towards Synthetic Data Generation for Characterization of FPGAs,” GOMACTech 2025 Proceedings, March 2025. Link to PDF.

E. Carlisle, J. Koiner, E. Ezell, S. Harper, “System-Level Fault Injection on Heterogenous System-on-Chips,” GOMACTech 2025 Proceedings, March 2025. Link to PDF.
J. Graf, M. Winslow, E. Drinkert, K. Urish, J. Hallman, “FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking,” GOMACTech 2025 Proceedings, March 2025. Link to PDF.

E. Carlisle, S. Harper, J. Graf, “Improving Workforce Development with Laboratory Automation,” 2024 IEEE Physical Assurance and Inspection of Electronics (PAINE) Conf., Nov. 12-14, 2024.

K. Paar, S. Harper, “Challenges and Mitigations for Data Remanance in FPGA Based Systems,” Ground Vehicle Systems and Technology Symposium (GVSETS), Aug 2024. Link to PDF.

S. Adams, M. Taylor, C. Crofford, S. Harper, W. Batchelor, W. Headley, “Exploring Explainable AI Techniques for Radio Frequency Machine Learning,” IEEE International Conference on Machine Learning for Communication and Networking (ICMLCN), May 2024. Link to paper.

“Automating Hardware Trojan Insertion for Producing a Trusted & Assured Microelectronics Benchmark Dataset,” J. Koiner, K. Paar, M. Blacconiere, M. Winslow, S. Harper, J. Graf, DoD Anti-Tamper Conference, April 2024.

“The Role of EDA in FPGA Assurance Best Practices,” M. Winslow, J. Graf, W. Batchelor, S. Harper, K. Paar, A.A. Sohanghpurwala, GOMACTech 2024, March 2024. Link to PDF.
“Non-Destructive Evaluation of Repackaged Counterfeit FPGAs via Machine Learning,” W. Batchelor, J. Koiner, C. Crofford, K. Paar, M. Winslow, M. Taylor, S. Harper, GOMACTech 2024, March 2024. Link to PDF.

“Attest: Non-Destructive Identification of Counterfeit FPGA Devices,” W. Batchelor, J. Koiner, C. Crofford, K. Paar, M. Winslow, M. Taylor, S. Harper, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), Oct 2023. Link to paper.

"Generating Statistically Relevant Trojan Benchmarks for Microelectronics Quantifiable Assurance," M. Winslow, W. Bachelor, J. Koiner, K. Paar, S. Harper, and J. Graf, GOMAC 2023. Link to PDF.
"Determining Residual Risk from Optimized Selection of Hardware Trojan Detection Strategies," Z. A. Collier, W. Batchelor, M. Winslow, S. Harper, and J. Graf, GOMAC 2023. Link to PDF.
"Facilitating Assurance and Collaboration through Digital Threads in Microelectronics Experiments," E. Carlisle IV, S. Harper, and J. Graf, GOMAC 2023. Link to PDF.

“Anti-Tamper Implementation – An Irrefutable Logger in Microchip Polarfire Devices,” K. Paar, J. Graf, S. Harper, and T. Dunham, DoD Anti-Tamper Conference 2022.
“Modernizing FPGA Design Assurance Software,” J. Graf, S. Harper, A. A. Sohanghpurwala, and E. Carlisle, DoD Anti-Tamper Conference 2022.

“Modernizing FPGA Design Assurance Software,” J. Graf, S. Harper, A. A. Sohanghpurwala, and E. Carlisle, GOMAC 2022. Link to PDF.
“Advancing Strategy Selection for Hardware Trojan Detection with Subrational Behavior Models,” W. Batchelor, M. Winslow, C. Crofford, M. Blacconiere, S. Harper, J. Graf, GOMAC 2022. Link to PDF.
“Trace: Towards a Traceable Microelectronics Implementation Flow,” A. A. Sohanghpurwala, C. Fraley, J. Graf, S. Harper, GOMAC 2022. Link to PDF.
“Automated Analysis of a Thermally Triggered FPGA Hardware Trojan,” E. Carlisle, S. Harper, J. Koiner, K. Paar, M. Capone, and J. Graf, GOMAC 2022. Link to PDF.

“GameRunner: Automating Analysis and Optimization of Microelectronics Trust with Game Theory,” E. Carlisle, J. Graf, W. Batchelor, S. Harper, GOMAC 2021. Link to PDF.
“IP Integrity Flow: Ensuring IP Integrity in FPGA Synthesis,” A. A. Sohanghpurwala, C. Fraley, S. Harper, J. Graf, A. Cook, T. Dunham, GOMAC 2021. Link to PDF.
“DELV: Datasheet/English to Logic Verification,” E. Carlisle, J. Koiner, S. Frederiksen, J. Graf, S. Harper, J. Aromando, and M. Hsiao, GOMAC 2021. Link to PDF.

“A practical application of game theory to optimize selection of hardware Trojan detection strategies,” J. Graf, W. Batchelor, S. Harper, R. Marlow, E. Carlisle, and P. Athanas, HaSS Journal, December 2019. Link to Springer website.

“Introducing a Trust Metric Foundation and Deriving Trust-for-Buck,” S. Harper, J. Graf, W. Batchelor, T. Dunham, and P. Athanas, GOMAC 2019. Link to PDF.

"Hardware Trojan Detection using Xilinx Vivado", R. Marlow, S. Harper, W. Batchelor, J. Graf, in IEEE National Aerospace and Electronics Conference (NAECON), July 2018. Link to PDF.

“Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems,” S. Harper, J. Graf, M.A. Capone, J. Eng, M. Farrell, L.W. Lerner, in IEEE National Aerospace & Electronics Conference (NAECON), June 2017. Link to PDF.

“Irrefutable Tamper Logging through FPGA Key Management,” J. Graf, A. A. Sohanghpurwala, M. French, and A. Schmidt, in DoD AT Conference Proceedings, April 2017.

“Private Verification for FPGA Bitstreams,” J. Graf and A. A. Sohanghpurwala, in GOMACTech 2017 Proceedings, March 2017. Link to PDF.
“OpTrust: Software for Determining Optimal Test Coverage and Strategies for Trust,” J. Graf, in GOMACTech 2017 Proceedings, March 2017. Link to PDF.

“Towards System-Level Adversary Attack Surface Modeling for Microelectronics Trust,” J. Graf, in IEEE National Aerospace and Electronics Conference (NAECON), July 2016. Link to PDF.

“Trust Games: How Game Theory Can Guide the Development of Hardware Trojan Detection Methods,” J. Graf, in Hardware Oriented Security and Trust (HOST), 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2016. Link to PDF.

“Toward Optimal Hardware Trojan Detection through Security Economics and Game Theory,” J. Graf, in GOMACTech 2016 Proceedings, March 2016, paper 14.4. Link to PDF.