PV-Bit Verification
User-driven verification of FPGA bitstreams
Enverite® PV-Bit® verification evaluates the equivalence of an FPGA bitstream and its physical netlist. The FPGA configuration bitstream is the only design representation that is actually deployed; however, existing verification tools are only able to verify publicly documented formats such as simulation netlists and HDL source code.
Graf Research® Corporation has leveraged our relationships with FPGA vendors along with a unique, patented technical approach to create Enverite® PV-Bit® verification, which allows the end-user to ensure their FPGA bitstream implementation matches that of the publicly documented and formally verifiable post place-and-route (PAR) simulation netlist.
Our unique, patented technical approach fills a gap in high assurance verification flows for security and functional safety by allowing an end-user to independently verify the functionality of their FPGA bitstream without reverse engineering.
PV-Bit verification respects FPGA vendor and third-party vendor IP
PV-Bit® verification evaluates the contents of the vendor-proprietary bitstream while respecting FPGA vendor IP and third-party vendor IP. Instead of reverse-engineering the bitstream to HDL, PV-Bit® verification performs an encapsulated comparison of the physical netlist and the bitstream. Once this process is complete, a report is generated for the user.
Enverite PV-Bit Demonstration
PV-Bit verification helps you follow NSA guidance on FPGA assurance
The FPGA assurance guidelines released by NSA provide a list of mitigations against the introduction of Trojans during design development. One of these mitigations, Select a proof process, helps protect against an adversary that compromises the design cycle. The mitigation description is as follows:
Use logical equivalency checking to the greatest extent possible. Equivalency checking is used to prove the tools did not modify the logic or configuration settings. To do this, the final bitstream is compared to the originating application HDL to demonstrate they are logically equivalent with no extraneous logic in the final format. This approach confirms Trojans were not inserted during the implementation steps. This check also confirms configuration settings are maintained and not altered.
PV-Bit® verification helps you comply with this guideline by allowing you to verify the contents of your bitstreams against the final placed-and-routed (PAR) netlist generated from your build tools. If this post-PAR netlist is then compared to the source HDL using a commercial logic equivalence checking tool, the NSA suggested best practice is met.
More Information
Use the Request Documents form to request the PV-Bit® whitepaper as well as other relevant documents.
If you’d like to contact us about using PV-Bit® verification, or if you wish to see a product demonstration or have a product support question, contact us.