We’re presenting three papers at GOMAC next week! It’s the most papers the company has ever had accepted to the conference in a single year—well done, team! In these papers, we are publicly announcing two new technologies for the first time and updating a third, presented by Dr. Edward Carlisle IV and Dr. Ali Asgar Sohanghpurwala. Be sure to check them out! They are:
1. "DELV: Datasheet/English to Logic Verification" (Session 3, Tuesday March 30)
2. "IP Integrity Flow: Ensuring IP Integrity in FPGA Synthesis" (Session 27, Thursday April 1)
3. "GameRunner: Automating Analysis and Optimization of Microelectronics Trust with Game Theory" (Session 38, Thursday April 1)
To learn more about them, take a look at the abstracts below!
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GameRunner: Automating Analysis and Optimization of Microelectronics Trust with Game Theory
Edward Carlisle IV, Jonathan Graf, Whitney Batchelor, Scott Harper
Abstract: This work presents GameRunner, a software tool to automate the process of recommending and applying an optimal hardware trojan horse detection strategy using our game theoretic analysis framework, OpTrust. GameRunner takes as inputs economic incentives and empirically derived test data and outputs optimal strategies for applying trojan detection methods. These strategies, or prescriptions, can be applied to a Jenkins workflow to automate the process of applying an optimal trojan detection method during a microelectronics design process. GameRunner also provides visualizations to aid in the analysis of the impact of input variables on game results. The architecture of the software tool is discussed along with examples of the novel analysis techniques and insights it enables.
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IP Integrity Flow: Ensuring IP Integrity in FPGA Synthesis
Ali Asgar Sohanghpurwala, Carlton Fraley, Scott Harper, Jonathan Graf, Alan Cook, Tim Dunham
Abstract: This work introduces the IP Integrity Flow (IIF), a solution that integrates with existing commercial EDA flows to provide a mechanism for auditing and verifying the integrity of IP that is included in an FPGA design throughout the synthesis flow and into deployment. The IIF approach was broken into three development objectives. The first objective was to define an IP isolation flow based on existing vendor tool functionality. The second objective was to develop a signature and authentication process where design artifacts are cryptographically signed at all stages of the implementation flow in a manner that enables both IP verification, tamper-resistant record keeping, and audit functionality based on cryptographically secure signatures. The third objective was to develop verification mechanisms that can determine whether specific isolated and authenticated IP is present in the final configuration bitstream. The approach described below accomplishes these objectives in a way that permits use of the signed artifacts throughout the entire synthesis flow – from HDL to bitstream, as well as into design deployment. A set of software tools was developed to augment the Xilinx implementation flow with secure signature, authentication, IP validation, and auditing capabilities. The objectives and architecture of the software are discussed here along with the secure, auditable workflows enabled by the IIF.
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DELV: Datasheet/English to Logic Verification
Edward Carlisle IV, James Koiner, Steven Frederiksen, Jonathan Graf, Scott Harper, John Aromando, Michael Hsiao
Abstract: This work presents the Datasheet/English to Logic Verification (DELV) tool, software that automates the process of generating verifiable statements from a design specification and performing logic verification. Our prototype extracts the contents of a PDF datasheet and formats them for consumption by our custom natural language engine. The DELV language engine then produces an intermediate representation for properties and actions defined in the datasheet. These properties are converted to SystemVerilog Assertions and evaluated against the design implementation. Our approach applies novel forms of normalization and leverages an extensible commonsense knowledge base of semantic mappings to support the wide range of complex natural language commonly found in datasheets.
