Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Graf Research CEO, Dr. Jonathan Graf, is presenting alongside Kevin Urish from Siemens on the topic “Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream.” They cover how Enverite PV-Bit verification takes safety and security compliance evidence provided by Siemens EDA software and proves those claims hold in the final bitstream implementation. The webinar is presented live on Wednesday, February 19th! Register for the webinar at this link.